Safe machine learning accelerator and interconnect design

Recently Machine Learning (ML) accelerator has grown into prominence with significant power-performance efficiency improvements over CPU or GPU. Network-on-chip (NoC) was proposed to deliver fast, reliable and scalable communication between various on-chip IPs including CPU, GPU and hardware accelerators. Both ML accelerator and NoC are critical components of the heterogeneous computing system design. On the other hand, Aggressive technology scaling poses new problems of permanent and transient faults. Functional safety is the top priority for automotive and other mission-critical system design. Safety designs emphasize on high error detection coverage with the safe state to recover within Fault Tolerant Time Interval (FTTI). With more functionality and performance features packed into a safety chip design, die size grows, and power consumption becomes a limiting factor in meeting system thermal requirements. Various Concurrent Error Detection (CED) techniques were proposed to detect permanent and transient errors of hardware design with different strength and capability which can be characterized with a set of defined metrics including coverage, latency, localization and Power Performance Area (PPA) efficiency. However, few of them were proven or applicable for safety design with stringent error detection coverage requirements. Therefore, Dual Modular Redundancy (DMR) is still commonly used in the industry to provide robust error detection but with a large area and power penalty. In this dissertation, we studied area and power efficient safety design for robust CED and error recovery of ML accelerator and NoC interconnect. In Chapter 2 and 3, we proposed algorithm based error checking and correction techniques for a Convolutional Neural Network (CNN) accelerator and demonstrated that we could achieve high Diagnostic Coverage (DC) safety goal with minimal area, power and run-time error recovery overhead and without performance degradation. In Chapter 4, we developed a new partition optimized packet-level run-time error detection technique for NoC network, and in Chapter 5, we applied a combination of partial duplication, Error Detection Code (EDC) and invariance checking techniques for Network Interface (NI) to meet high DC safety requirement with minimal power and area overhead.Electrical and Computer Engineerin