This paper presents a new scheme for the hardware evaluation of functions in fixed-point format, for precisions up to 30 bits. This scheme yields an architecture made of four look-up tables, a multi-operand adder, and two small multipliers. This new method is evaluated and compared with other published methods.Cet article présente un nouvel algorithme pour l’évaluation de fonctions en virgule fixe, pour des précisions allant jusqu’à 30 bits. Cet algorithme est basé sur une architecture composée de 4 lectures de tables, un additionneur multiopérandes et de deux petits multiplieurs. Cette nouvelle méthode est évaluée et comparée avec de précédents algorithme
This paper presents a core generator for arbitrary numeric functions on Xilinx Virtex FPGAs. The cor...
International audienceLinear (order-1) function evaluation schemes, such as bipartite and multiparti...
International audienceA unified view of most previous table-lookup-and-addition methods (bipartite t...
(eng) This paper presents a new scheme for the hardware evaluation of functions in fixed-point forma...
This paper presents a new scheme for the hardware evaluation of functions in fixed-point format, for...
(eng) Many general table-based methods for the evaluation in hardware of elementary functions have b...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
(eng) This paper presents a new scheme for the hardware evaluation of elementary functions, based on...
Cet article a obtenu le "best paper award" de la conférenceInternational audienceSolving the Table M...
This paper presents a new scheme for the hardware evaluation of elementary functions, based on a pie...
International audienceMany applications require the evaluation of some function through polynomial a...
This paper presents a core generator for arbitrary numeric functions on Xilinx Virtex FPGAs. The cor...
International audienceLinear (order-1) function evaluation schemes, such as bipartite and multiparti...
International audienceA unified view of most previous table-lookup-and-addition methods (bipartite t...
(eng) This paper presents a new scheme for the hardware evaluation of functions in fixed-point forma...
This paper presents a new scheme for the hardware evaluation of functions in fixed-point format, for...
(eng) Many general table-based methods for the evaluation in hardware of elementary functions have b...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
Many general table-based methods for the evaluation in hardware of elementary functions have been pu...
(eng) This paper presents a new scheme for the hardware evaluation of elementary functions, based on...
Cet article a obtenu le "best paper award" de la conférenceInternational audienceSolving the Table M...
This paper presents a new scheme for the hardware evaluation of elementary functions, based on a pie...
International audienceMany applications require the evaluation of some function through polynomial a...
This paper presents a core generator for arbitrary numeric functions on Xilinx Virtex FPGAs. The cor...
International audienceLinear (order-1) function evaluation schemes, such as bipartite and multiparti...
International audienceA unified view of most previous table-lookup-and-addition methods (bipartite t...