Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

International audienceIn this letter, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using non intentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapor Deposition (CVD) using the Vapor-Liquid-Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behavior with a threshold voltage at room temperature around-1.15 V, a high ION/IOFF ratio up to 10 6 with a low IOFF current about 1 pA, a maximum transconductance (gm,max ~ 0.9 µS at VGS =-0.65 V and VDS = 1 V) and a minimum inverse subthreshold slope around 145 mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture