Low-Latency Energy-Recovery Circuitry.

Voltage scaling has diminished with each advancement in process technologies, making power dissipation one of the primary design considerations for modern digital systems across all market segments. This dissertation describes a novel charge-recovery logic family and a resonant-clocked dynamic logic that utilize energy-recovery techniques to recycle charge from the system, effectively reducing dynamic power dissipation. We propose a novel charge-recovery logic, called Enhanced Boost Logic, which achieves high efficiency and high performance operation through the use of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. Fabricated using a 0.13μm technology with a 3nH on-chip inductor, a 14-tap 8-bit FIR filter implemented using Enhanced Boost Logic achieves operating frequency up to 600MHz with only 1.5 cycles of latency overhead compared to a static CMOS implementation. At its natural frequency of 466MHz, the FIR dissipates 39.1mW. With a figure of merit equal to 93.6nW/MHZ/Tap/InBit/CoeffBit, it achieves 29% improvement compared to previously reported FIR filter test-chips with equal or greater sampling rate than our design at its 466MHz resonant point. We also propose a dynamic logic family, call Dynamic Evaluation Static Latch, synchronized by a two-phase resonant clock, which achieves dynamic-logic levels performance with significant power reduction. Fabricated in a 90nm technology with an 0.41nH integrated inductor, a resonant-clocked FPU implemented using this methodology achieves clock speeds up to 2.07GHz. At its resonant frequency of 1.81GHz, it dissipates 334mW, yielding 31.5% lower power and 32% more GFLOPS/W over a conventionally-clocked version of the same FPU implemented on the same die. Relying on circuit, logic, and architectural optimizations, the resonant-clock FPU breaks new ground along several metrics. Specifically, with a total area of 0.391mm2 including the on-chip inductor, it occupies the smallest footprint among competing stat-of-the-art reduced-latency FPUs. Moreover with an overall latency of 64 FO4, it achieves the shortest overall latency among state-of-the-art reduced-latency FPUs. Delivering 10.82GFLOPS/W, this resonant-clock FPU achieves the highest energy efficiency among state-of-the-art continuously data-streaming FPUs.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86457/1/jckao_1.pd