silicon nanowires synthesis using top down and bottom up approaches : applications to chemical sensors

International audienceTwo types of SiNWs are synthesized, without requiring costly lithographic tools, following the VLS growth technique (bottom up approach), and the sidewall spacer realization (top down approach). Au-catalyst VLS SiNWs were synthesized and integrated into resistors and field effect transistors. In this way, a heavily phosphorous in-situ doped polysilicon layer was first deposited by LPCVD (Low Pressure Chemical Vapor Deposition) on a substrate capped with a SiO2 buffer layer. This film was patterned by Reactive Ion Etching (RIE) to define the geometry of the comb shape electrodes (interdigitated structure). Au thin film ( 5 nm) was then deposited by thermal evaporation and locally removed using a lift off technique in order to define precise location for SiNWs growth. High density Au-catalyst non intentionally doped VLS-SiNWs network was then synthesized by LPCVD technique at 480°C and 40 Pa using silane (SiH4) as precursor gas. Due to the length of the SiNWs, which can exceed 20 µm, bridges and contacts between SiNWs ensure the connection of these two heavily doped polysilicon islands leading to the formation of devices in a 3D configuration. This synthesis results in a tangled growth of 100 nm diameter SiNWs insuring electrical contact between the two doped electrodes. The sidewall spacer method is an alternative way to synthesize SiNWs in a 2D configuration. At first, a dielectric film is deposited and patterned into islands by conventional UV lithography. Then, an undoped amorphous silicon layer is deposited by LPCVD at 550°C and 90 Pa, and crystallized by thermal annealing under vacuum at 600°C during 12 hours. Accurate control of this polysilicon layer RIE rate leads to the formation of nanometric size sidewall spacers that can be used as nanowires. Polysilicon NWs with a 100 nm or 50 nm curvature radius are the synthesized and integrated into coplanar structure (resistors, TFT). These two types of SiNWs based devices are integrated into low temperature (