Applications of Nanoelectronic Technology to Image Processors, Velocity-Tuned Filters and Crossbar Memories

It is widely expected new devices and architectures will have to be developed to sustain the relentless performance scaling trend the CMOS industry has enjoyed in the last 30 years. In this thesis, we demonstrate several nanoelectronics implementations that offer much higher information throughput than their CMOS counterparts. Chapter 1 provides the motivation and background information for the implementations including image processors, velocity-tuned filters and crossbar memories. In Chapter 2, color image processors based on multi-peak resonant tunneling diodes are discussed. The multi-peak resonant tunneling diodes can be configured into a two-dimensional array of regular computing elements, locally connected by programmable passive and active elements with a view to realize a wide gamut of color image processing functions such as quantization, color extraction, image smoothing, edge detection and line detection. In order to process color information of the input images, two different methods for color representation schemes were discussed: one using color mapping, and the other using direct RGB representation. Finally, we demonstrate image functions through HSPICE simulation using these methods on the proposed nano-architecture. In chapter 3, we propose a nanoscale velocity-tuned filter that employs resonant tunneling diodes to perform temporal filtering to track moving and stationary objects. The new velocity-tuned filter is not only amenable for nanocomputing, but also superior to other approaches in terms of area, power and speed. We show that the proposed nanoarchitecture for velocity-tuned filter is asymptotically stable in the specific region. In chapter 4, we electrically modeled a crossbar memory cell and designed specific peripheral circuitry, including the column and row decoders, a sensing circuitry for detecting the difference in the resistance of the cell, and the control circuit for reading and writing. An analytical model on static power dissipation was conducted to suggest optimal design for power dissipation. To improve the area overhead, we introduced MUX logics to reduce the numbers of sense amplifiers attached to all the bit lines. In addition, methods to address the size mismatch between crossbar memory arrays and CMOS peripheral circuitry in the crossbar memory design are discussed.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/62279/1/leewh_1.pd