Add to ORKGA self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are fabricated. Minority carrier life-time and breakdown voltage are not affected
A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hol...
Currently, the established large area technology is amorphous silicon where device performance is sa...
Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of research...
A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and sm...
This paper investigates a low damage reactive ion etch (RIE) process to make thin silicon nitride si...
This letter reports the implementation of the bottom-gate MOSFET, which possesses the following full...
A new process flow to realize the ideal self-aligned double-gate (DG) MOSFET was designed. The ideal...
This paper reports the implementation of the bottomgate MOSFET which possesses the following fully-s...
A process for fabricating a device based on tunneling through a very thin vertical silicon membrane ...
In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-ga...
In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-ga...
In this paper, a lithography independent gate definition technology to fabricate sub-100nm device is...
In this paper, a lithography independent gate definition technology to fabricate sub-100nm device is...
Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate place...
In the context of transistor size miniaturization the motivation of this work was focused on the fab...
A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hol...
Currently, the established large area technology is amorphous silicon where device performance is sa...
Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of research...
A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and sm...
This paper investigates a low damage reactive ion etch (RIE) process to make thin silicon nitride si...
This letter reports the implementation of the bottom-gate MOSFET, which possesses the following full...
A new process flow to realize the ideal self-aligned double-gate (DG) MOSFET was designed. The ideal...
This paper reports the implementation of the bottomgate MOSFET which possesses the following fully-s...
A process for fabricating a device based on tunneling through a very thin vertical silicon membrane ...
In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-ga...
In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-ga...
In this paper, a lithography independent gate definition technology to fabricate sub-100nm device is...
In this paper, a lithography independent gate definition technology to fabricate sub-100nm device is...
Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate place...
In the context of transistor size miniaturization the motivation of this work was focused on the fab...
A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hol...
Currently, the established large area technology is amorphous silicon where device performance is sa...
Double-gate MOSFETs have the most ideal device structure, and are drawing the attentions of research...