Towards a dependable homogeneous many-processor system-on-chip

Nowadays, dependable computing systems are widely required in mission-critical applications. While the advance in CMOS technology enables smaller and faster circuits, the dependability of modern ICs has worsened as a result of the shrinking dimensions of MOS transistors and the increasing complexity of semiconductor devices. \ud \ud In this thesis, the three important dependability attributes of an MPSoC, being reliability, availability and maintainability are examined. The possible approaches to enhance these attributes are explored. The reliability of an MPSoC can be improved by using processor cores as spare. Maintainability can be realized by incorporating fault detection and self-repair features into an MPSoC. By dynamically detecting faults and reconfiguring the system to circumvent them, the system can be regarded as functionally correct with a possible drop in performance. Faster fault detection and repair operations will enable a highly available MPSoC. \ud \ud The proposed dependability approach is implemented in silicon by incorporating an infrastructural IP (the dependability manager) into a homogeneous MPSoC platform with multiple Xentium processing tiles. The cost of the chosen dependability approach in terms of performance and resource (silicon area/energy) overhead are evaluated and its effectiveness is assessed using experiments and actual measurement results