Decomposed software pipelining for VLIW with precedence delays and resource constraints

International audienceWe consider the problem of scheduling loops on VLIW architectures used in embedded systems. We address the cyclic problem of finding periodic schedules with minimal period taking into account all constraints induced by uniform data dependencies and pipelined functional units. A guaranteed approach, called decomposed software pipelining (DSP), is extended to consider the above constraints. A theoretical worst case ratio is evaluated and the practical interest of DSP is established using real VLIW architecture (ST200 of STMicroelectronics) and a benchmark of graphs issued from ST compiler