Carry-Look-Ahead Adder in Multiple-Valued Recharge Logic

In the last few decades, multiple-valued logics have been proposed as a possible alternative or enrichment to binary logic. Multiple-valued circuits replace the two states of binary logics with finite or infinite sets of values. Many multiple-valued circuits, both current-mode and voltage-mode, have been published. To the best of our knowledge very few of these have had commercial success. However, multiple-valued recharge logics show great potential, reducing the number of transistors needed to perform a logic operation considerably when compared to binary logic. Present multiple-valued recharge adders use an inefficient carry-handling, and thus setting limitations of the number of bits that can be represented, as well as the max operation frequency. In this thesis a multiple-valued recharge adder making use of carry-look-ahead (CLA) is presented, addressing the carry-ripple problem. Furthermore, the presented multiple-valued CLA recharge adder is used in a proposed 16-bit CLA scheme. The CLA scheme is compared to a 16-bit multiple-valued recharge adder, regarding gate-delay, maximum operation frequency, and power consumption. Limitations of the proposed design is also presented