Multi-Path Ageing Sensor for Cost-efficient Delay-Fault Prediction

Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow progressive degradation in the performance of MOS transistors. Consequently, the speed of a chip can significantly degrade over time; this results in delay faults. Dynamic reliability management schemes have been proposed to assure an IC's lifetime reliability. Such schemes are typically based on the use of ageing sensors to predict a circuit's failure before errors actually appear. Existing ageing sensors are usually placed on the circuit's longest delay paths, which are deemed to be the most vulnerable to delay faults. Such an approach is very costly and may be infeasible in today's complex designs that typically have a large number of long delay paths that need to be monitored. This work proposes a new ageing sensor capable of monitoring multiple paths concurrently. The proposed sensor has been implemented and verified in 90nm technology. Our results indicate that the use of the proposed sensor for delay monitoring of the EX stage in a 32-bit MIPS can lead to a significant saving in area overheads of 70.8% and 53% compared to Razor and Canary respectively