Static Aging Analysis Using 3-Dimensional Delay Library

The growing concern about time-dependent performance variations of CMOS devices due to aging-induced delay degradation has increased with shrinking technology dimensions of the devices . One of the main causes of aging is Negative Bias Temperature Instability (NBTI). Modeling NBTI-induced delay at gate level depends on the real stress activity of gate inputs which are related to the workload applied from the higher level of abstraction (e.g. Application). Having estimated values about the degradation delays can make design stage to consider this issue as a design constrain and even to precisely allocate the online aging sensors. this paper propose a method to include the stress probability within technology library as three dimensional look-up tables for Static Timing Analysis(STA) process of the design as an approach named Static Aging Analysis(SAA). the purpose of this approach is instead of estimating only the timing delay at time zero, estimating NBTI-induced delays for predefined lifetime of the product