Cost-effective radiation hardened techniques for microprocessor pipelines

The aggressive scaling of semiconductor devices has caused a significant increase in the soft error rate induced by radiation particle strikes. This has led to an increasing need for soft error tolerance techniques to maintain system reliability, even for sea-level commodity computer products. Conventional radiation-hardening techniques, typically used in safety-critical applications, are prohibitively expensive for non-safety-critical microprocessors in terrestrial environments. Providing effective hardening solutions for general logic in microprocessor pipelines, in particular, is a major challenge and still remains open. This thesis studies the soft error effects on modern microprocessors, with the aim to develop cost-effective soft error mitigation techniques for general logic, and provide a comprehensive soft error treatment for commercial microprocessor pipelines.This thesis presents three major contributions. The first contribution proposes two novel radiation hardening flip-flop architectures, named SETTOFF. A reliability evaluation model, which can statistically analyse the reliability of different circuit architectures, is also developed. The evaluation results from 65nm and 120nm technologies show that SETTOFF can provide better error-tolerance capabilities than most previous techniques. Compared to a TMR-latch, SETTOFF can reduce area, power, and delay overheads by over 50%, 86%, and 78%, respectively. The second contribution proposes a self-checking technique based on the SETTOFF architectures. The self-checking technique overcomes the common limitation of most previous techniques by realising a self checking capability, which allows SETTOFF to mitigate both the errors occurring in the original circuitry, and the errors occurring in the redundancies added for error-tolerance. Evaluation results demonstrated that the self-checking architecture can provide much higher Multiple-Bit-Upsets tolerant capabilities with significantly less power and delay penalties, compared to the traditional ECC technique, for protecting the register file. The third contribution proposes a novel pipeline protection mechanism, which is achieved by incorporating the SETTOFF-based self-checking cells into the microprocessor pipeline. An architectural replay recovery scheme is developed to recover the relevant errors detected by the self-checking SETTOFF architecture. The evaluation results show that the proposed mechanism can effectively mitigate both SEUs and SETs occurring in different parts of the pipeline. It overcomes the drawback of most previous pipeline protection techniques and achieves a complete and cost effective pipeline protection.