Generation of Ordered Sub-circuits for an Automatic Sizing Program

The design of increasingly complex integrated circuits requires synthesis tools rather than analysis tools. A tool that calculates transistor sizes is useful both to design a new circuit and to move an existing design to another process. The paper describes an algorithm that can be used in such a program to structure an otherwise unstructured array of unsized transistors in a CMOS digital circuit. This structure is related to the functionality of the circuit, so that the sizing model is provided with all the information required. The paper then goes on to discuss how the `subcircuits' were ordered so that they could be sized, taking the necessary factors into accoun