A method for sizing transistors in CMOS op-amps

The authors present a method for automatically calculating the size of the transistors and passive components in a CMOS op-amp given the specification and loading of the op-amp. The method is similar to that used in the OASYS program in that it uses no simulation. Like the OASYS method, the authors estimate the sizes and then calculate the parasitics. The parasitics calculated are then used to recalculate the sizes. This process continues until the parasitics change only little. Unlike OASYS, the authors separated the sizing method from the model of the transistor. This means one is able to use any transistor model to size the transistors, and, because the method does not use simulation and so makes less calls of the model equations, the model used can be more complicated than that used for simulatio