Migratory Memory-Side Processing Breakthrough Architecture for Graph Analytics

Presented on November 2, 2018 at 1:45 p.m. the Klaus Advanced Computing Building, Room 1116 East/West, Georgia Institute of Technology (Georgia Tech).Second Annual Center for Research into Novel Computing Hierarchies (CRNCH) Summit, November 2, 2018 at Georgia Tech.Keynote Speaker - Dr. Peter Kogge is a Chaired Professor in Notre Dame's Department of Computer Science and Engineering. Peter is an IBM Fellow and the 2012 Seymour Cray Award winner among other awards. Prior to academia, he spent 26 yrs. with IBM Federal. Peter's undergraduate degree is from Notre Dame and he has a Ph.D. from Stanford in Electrical Engineering.Runtime: 40:52 minutesToday's data intensive applications, such as sparse-matrix linear algebra and graph analytics, do not exhibit the same locality traits as compute-intensive applications, resulting in the latency of individual memory accesses overwhelming the advantages of deeply pipe-lined fast cores. The Emu Migratory Memory-Side Processing architecture provides a highly efficient, fine-grained memory system and migrating threads that move the thread state as new memory locations are accessed, without explicit program directives. The "put-only" communication model dramatically reduces thread latency and total network bandwidth load as return trips and cache coherency are eliminated. Working with the CRNCH team, Emu shares results that validate the viability of the architecture, presents a roadmap for scalability and discusses how the architecture delivers orders of magnitude reduction in data movement, inter-process communication and energy requirements. The talk touches on the familiar programming model selected for the architecture which makes it accessible to programmers and data scientists, and reveals upcoming areas of joint research with Georgia Tech in the area of Migratory Threads