Negative Capacitance Technology for Ultra-low Power Computing

Presented at the Nano@Tech Meeting on August 23, 2017 at 12:00 p.m. in the Marcus Nanotechnology Building, Rooms 1117-1118, Georgia Tech.Asif Khan received his Ph.D. in electrical engineering and computer sciences from the University of California, Berkeley in 2015 and his B.S. degree in electrical and electronic engineering from Bangladesh University of Engineering and Technology (BUET) in 2007. He joined the School of Electrical and Computer Engineering at the Georgia Institute of Technology as an assistant professor in 2017. Dr. Khan’s interests lie at the intersection of electrical engineering, materials science, and the physics of computation. Computing nanodevices that leverage new physics and phenomena in emerging material systems (such as ferro-/anti-ferroelectrics, multiferroics, complex and transition metal oxides and correlated electron systems) are the mainstay of his group. The end goal of his research is to synergize these device-level innovations with existing or new circuits, architectures, and systems concepts such that classical limitations of CMOS platforms can be transcended and new computing paradigms can be envisioned. His work led to the first experimental proof-ofconcept demonstration of the negative capacitance – a novel physical phenomenon that can lead to ultra-low power computing and memory platforms by overcoming the fundamental "Boltzmann Limit" of 60 mV/decade subthreshold swing in field-effect transistors. Dr. Khan received the Qualcomm Innovation Fellowship in 2012, the Silver prize at the 5th Taiwan Semiconductor Manufacturing Company (TSMC) Outstanding Student Research Award in 2011, the University Gold medal from BUET in 2011, Kintarul Haque Gold Medal from BUET in 2011, the 1st prize in IEEE Region 10 Undergraduate Student Paper Contest in 2006, and the 2nd prize in the IEEE History Society Undergraduate Student Paper Contest in 2004.Runtime: 48:35 minutesNegative capacitance - an unusual physical phenomenon, where the stored charge decreases with an increasing voltage - can find interesting applications in electronics. For example, when used as the gate oxide in the MOSFET, a negative capacitance material can reduce the subthreshold swing below the fundamental physical limit of 60 mV/decades [1]. This device technology can, in turn, significantly lower the energy dissipation in CMOS circuits by enabling new pathways for arbitrarily reducing the power supply voltage. I will give an overview of the exciting developments in the field of negative capacitance over the past six years starting from the theoretical prediction in 2008 to the clean experimental demonstration of this phenomenon in archetypal ferroelectric oxides [2,3]. I will also discuss our recent experimental work on negative capacitance transistors [4] and energy and performance projections of circuits based on negative capacitance MOSFETs [5,6,7]References: [1] Salahuddin et al. "Use of negative capacitance to provide voltage amplification for low power nanoscale devices." Nano Letters 8, 405 (2008). [2] Khan et al. “Negative capacitance in a ferroelectric capacitor.” Nature Mater. 14, 182 (2015). [3] Khan et al. “Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures.” Appl. Phys. Lett. 99, 113501 (2011). [4] Khan et al. “Negative capacitance in short-channel FinFETs externally connected to an epitaxial ferroelectric capacitor.” IEEE Electron Dev. Lett. 367, 111 (2016). [5] Khan et al. “Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation.” Proc. IEEE Electron Devices Meeting (IEDM), pp. 11-3 (2015). [6] Khandelwal, S., et al. "Circuit performance analysis of negative capacitance FinFETs." Proc. IEEE Symp. VLSI Technology (2016). [7] Samal et al. “Full chip power benefits with negative capacitance FETs.” Proc. ISLPED (2017)