Using small spacecrafts for a wide range of research and applied purposes is one of the major trends in the aerospace field. Modular-network architectures implemented on the “system-on-chip” hardware platform provide required characteristics of onboard control systems. Selecting this system architecture significantly increases demands on very large-scale integration (VLSI) design efficiency and project solution quality. In this paper, we propose a new approach to VLSI high-level synthesis based on a functional-flow parallel computing model. The modified VLSI design flow uses a functional-flow parallel programming language Pythagoras, which allows describing a VLSI operation algorithm with the maximal degree of parallelism. An offered interm...
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Mar...
The first step in high level synthesis consists of translating a behavioral specification into its c...
High level synthesis describes the process by which a behavioural description of a system is transla...
We develop methods and algorithms for a high-level synthesis and a formal verification of the archit...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
In this paper, we describe a comprehensive high-level synthe-sis system for control-flow intensive a...
The development, implementation and testing of a high-level synthesis system, for the automatic gene...
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system ...
We present a VLSI synthesis environment dedicated to the design of image processing architectures. T...
High-level synthesis has become commonplace in many areas of computing such as VLSI design and digit...
Contains reports on four research projects.U.S. Air Force - Office of Scientific Research (Contract ...
Executing a complex physical system model in real-time or faster has numerous applications in cyber-...
Recent progress in high-level synthesis (HLS) has helped raise the abstraction level of hardware des...
High Level Synthesis (HLS) provides a way to significantly enhance the productivity of embedded syst...
Abstract—This paper concerns automatic hardware synthesis from data flow graph (DFG) specification ...
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Mar...
The first step in high level synthesis consists of translating a behavioral specification into its c...
High level synthesis describes the process by which a behavioural description of a system is transla...
We develop methods and algorithms for a high-level synthesis and a formal verification of the archit...
In this paper, we describe a comprehensive high-level synthesis system for control-flow intensive as...
In this paper, we describe a comprehensive high-level synthe-sis system for control-flow intensive a...
The development, implementation and testing of a high-level synthesis system, for the automatic gene...
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system ...
We present a VLSI synthesis environment dedicated to the design of image processing architectures. T...
High-level synthesis has become commonplace in many areas of computing such as VLSI design and digit...
Contains reports on four research projects.U.S. Air Force - Office of Scientific Research (Contract ...
Executing a complex physical system model in real-time or faster has numerous applications in cyber-...
Recent progress in high-level synthesis (HLS) has helped raise the abstraction level of hardware des...
High Level Synthesis (HLS) provides a way to significantly enhance the productivity of embedded syst...
Abstract—This paper concerns automatic hardware synthesis from data flow graph (DFG) specification ...
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Mar...
The first step in high level synthesis consists of translating a behavioral specification into its c...
High level synthesis describes the process by which a behavioural description of a system is transla...