In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. Previously proposed memory scheduling algorithms are predominantly optimized for only one of these objectives: no scheduling algorithm provides the best system throughput and best fairness at the same time. This paper presents a new memory scheduling algorithm that addresses system throughput and fairness separately with the goal of achieving the best of both. The main idea is to divide threads into two se...
This paper describes a method to improve the cache locality of sequential programs by scheduling fin...
Chip multicore processors (CMPs) have become the default architecture for modern desktops and server...
Asymmetric or heterogeneous multi-core (AMC) architectures have definite performance, performance pe...
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently exec...
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory req...
In a chip multiprocessor (CMP) system, where multiple on-chip cores share a common memory interface,...
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The prop...
Modern chip multiprocessor (CMP) systems employ multiple memory controllers to control access to mai...
The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory ...
As thread level parallelism in applications has continued to expand, so has research in chip multi-c...
Transaction Memory systems may suffer from performance degradation when the concurrency level ...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...
This paper evaluates new techniques to improve performance and efficiency of Chip MultiProcessors (C...
In modern processors, the DRAM system is shared among concurrently-executing threads. Memory request...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...
This paper describes a method to improve the cache locality of sequential programs by scheduling fin...
Chip multicore processors (CMPs) have become the default architecture for modern desktops and server...
Asymmetric or heterogeneous multi-core (AMC) architectures have definite performance, performance pe...
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently exec...
DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory req...
In a chip multiprocessor (CMP) system, where multiple on-chip cores share a common memory interface,...
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The prop...
Modern chip multiprocessor (CMP) systems employ multiple memory controllers to control access to mai...
The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory ...
As thread level parallelism in applications has continued to expand, so has research in chip multi-c...
Transaction Memory systems may suffer from performance degradation when the concurrency level ...
Large, high frequency single-core chip designs are increasingly being replaced with larger chip mult...
This paper evaluates new techniques to improve performance and efficiency of Chip MultiProcessors (C...
In modern processors, the DRAM system is shared among concurrently-executing threads. Memory request...
Chip-level multiprocessors (CMP) have multiple processing cores (Cores) and generally have their cac...
This paper describes a method to improve the cache locality of sequential programs by scheduling fin...
Chip multicore processors (CMPs) have become the default architecture for modern desktops and server...
Asymmetric or heterogeneous multi-core (AMC) architectures have definite performance, performance pe...