Digital Calibration Method for High Resolution in Analog/RF Designs

Transistor random mismatch continuously poses challenges for analog/RF circuit design forachieving high accuracy and high yield as the process technology advances. Existing statisticalelement selection (SES) design method can improve transistor matching property, but it fallsshort of being a general calibration method due to its limited calibration range.In this dissertation, we propose a high resolution digital calibration method, called extendedstatistical element selection (ESES). As compared to the SES method, the ESES method not onlyprovides wider calibration range, but also it results in higher calibration yield with samecalibration resolution target. Two types of ESES based calibration application in analog/RFcircuits are also proposed. One is current source calibration and the other is phase/delaycalibration.To verify this proposed digital calibration method in circuit implementation, we designed,fabricated and tested a wideband harmonic rejection receiver design. The receiver utilizes ESESbasedgain and phase error calibration for improving harmonic rejection ratios. With the highcalibration resolution provided by the ESES method, after calibration, we achieved best-in-classharmonic rejection ratios. To extend the application of the proposed method, we further designeda current-steering D/A data converter (CS-DAC). The CS-DAC utilizes ESES-based amplitudeand timing error calibration for improving linearity performance. Simulation results showed thatwe can achieve more than one order of magnitude linearity improvement after performing ESESbasedcalibration in the CS-DAC