Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition

This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been designed and fabricated in a 28 nm CMOS technology. The prototype chip has been mounted on a printed circuit board with physical characteristics similar to the real application case and fully validated up to 1 Gb/s with input random patterns