Advantages of a vertical integration process in the design of DNW MAPS

This work discusses the main features of a CMOS Deep N-well (DNW) monolithic active pixel sensor (MAPS) fabricated in a vertically integrated technology, where two 130 nm CMOS homogeneous tiers are processed to obtain a 3D integrated circuit (3D-IC). The 3D CMOS MAPS, which was designed in view of vertexing applications to experiments at high luminosity colliders, features a 20 μm pitch for a point resolution of about 5 μm and data sparsification capabilities for high data rate systems. Results from the characterization of different test structures, including single pixels, 3×3 and 8×8 matrices, are presented. In particular, measurements have been performed with an infrared laser source to evaluate the charge collection properties of the proposed vertically integrated sensors