In-Network Data Processing using FPGAs

In recent years, network bandwidth has increased at a rapid pace, moving from 10G, to 40G/100G, to 400G. CPU frequency on the other hand has been stagnant. As a result, more and more CPU cycles have to be allocated to network processing to keep up with the increasing network bandwidth. At the same time, we have seen exponential growth in data requiring distributed systems to process it. While these systems benefit from the increased network bandwidth, their ability to scale out is limited by inefficiencies in I/O and data movement. Under the premise that most of such computation is distributed, one question remains as to whether data processing operations can be offloaded to the network. In this thesis, we explore two approaches to enable in-network data processing and thereby reduce burden on the CPU. Our first approach places data processing accelerators, such as FPGAs, in the network. To enable network-attached accelerators, we introduce a scalable network stack architecture for FPGAs supporting thousands of concurrent connections, a requirement of data center applications. Based on this architecture, we implement a TCP/IP stack that allows the seamless integration of accelerators into the existing network infrastructure. In our second approach, we enable data processing operations in the network by enhancing the functionality of the network card. In particular, we present Smart Remote Memory (STROM), which extends Remote Direct Memory Access (RDMA) with the capability to deploy acceleration kernels on the network card. These acceleration kernels can, for instance, directly access the remote host memory to traverse remote data structures such as lists or indexes. In addition to that, they can execute stream-based operations, e.g., filtering or aggregation, on data that is passing through the network card to the host memory, or vice versa. As part of this thesis, we implemented and released an open source TCP/IP stack for reconfigurable hardware. The stack enables network-attached accelerators and has been deployed successfully in a number of research and commercial systems. Following on from this success, we released an open source FPGA-based RDMA NIC, which we used as a prototyping platform for STROM, to facilitate more research in this area