Design and Implementation of Efficient VLSI Solutions for 3G and 4G Mobile Communications

In recent years, the global success of mobile communication devices (in particular, smartphones) has led to rapidly evolving mobile communication standards enabling ever higher data rates. Not only are new generations of standards being developed at a constantly increasing pace, the capabilities of existing standards are continuously enhanced via amendments and new releases. This puts a strain on the digital receiver implementation: the new functionality has to be supported while energy and silicon area remain equally limited. This thesis explores the design and implementation of digital baseband receivers, focusing two main application areas: 3G, the currently most widely deployed generation of mobile networks and LTE-Advanced, a highthroughput 4-th generation standard. First, TD-HSPA+, an enhanced 3G standard emerging from China, is considered. It serves as an example for the case where combatting intersymbol interference is critical for achieving efficient receivers. To this end, synchronization and equalization algorithms are developed and implemented in combination with an existing channel decoding chain to realize a TD-HSPA+ digital baseband ASIC. We then embed the ASIC into a complete physical layer system capable of receiving, processing and decoding RF signals from a basestation, proving that the developed concepts are truely applicable to the real world. Channel decoders are examined under the high-throughput conditions of LTE-Advanced, where turbo decoders present a major bottleneck with respect to the troughput of the digital baseband. Algorithmic and architectural optimizations lead to the first ever turbo decoder ASIC to achieve 1 Gbps throughput, which serves as a basis for a discussion of other parallelization options for future standards