Real-time network functions for the Internet of Things

The Internet of Things is evolving, more and more devices are getting connected, more data exchanged and increasingly complex tasks are handled by these net- works. Especially, low-power wireless communication networks are widely used due to the flexibility and fast deployment with a battery. The networks must be at low cost and still guarantee a long battery life time and compute a com- plex task. The goal of this thesis is to evaluate the outsourcing of a potentially complex task, e.g. real-time scheduling, to another processor and enable a real- time functionality for the whole network. The goal is a proof of concepts of the scheduler outsourcing by evaluating the implementation at the system-level, combining hardware, scheduler and network protocol. Many algorithms to support real-time functionalities are already developed, but the implementation for existing low-power systems with a single processor is difficult. Low power systems with a single core are often resource limited in memory and computational power. Multiple processors can be used to overcome this problem, but challenges with the interprocessor communication arises. The Dual-Processor Platform (DPP) enables a partition of the tasks between a very low-power communication processor (CP) and more powerful application processor (AP). The CP will be used to handle wireless communication based on the Low-power Wireless Bus (LWB), which is a best-effort network pro- tocol. The Blink scheduler is used to enable the real-time functionality in the network. The potentially complex and memory demanding Blink scheduler is outsourced to the AP. Further, the LWB round structure is adapted, which leverages the DPP platform and allows the computation of the next schedule on the AP while the communication is ongoing on the CP. Therefore, the delay for outsourcing the scheduler is becoming neglectable when the wireless network communication has sufficient many slots per round. In the end, the limitations like additional interprocessor communication delays are analysed and potential improvements are evaluated