Power Estimation on Electronic System Level using Linear Power Models

The modern everyday life involves a lot of mobile electronic devices, for example mobile phones and navigation systems. Over the last years, those devices have become smaller, faster and cheaper. However, the battery life time did not improve at the same rate. This makes power consumption one of the major design metrics for new electronic devices. The design decisions taken at early stages of system design have the highest impact on power consumption. Therefore, it is essential to obtain estimates already at Electronic System Level (ESL). However, power models are not generally available in most ESL tool suites. In particular, there is no established, largely automated method for creation of ESL power models. In order to alleviate this problem, an automated method for creation of ESL power models is proposed.The method is based on the assumption that there is an existing ESL simulator, a so-called Virtual Platform (VP), containing a model of the target component without support for power estimation. Additionally, there must be a way to obtain a reference power curve of this component in at least one scenario. The proposed method back-annotates the reference power information to the timed functional VP, thus creating an ESL power model. This power model can then be used in other scenarios and VPs. The power estimation method uses a linear power model. The activities in certain parts of the timed functional ESL model are traced. Those traces are multiplied with so-called power model factors in order to obtain the power estimate over time as a linear combination of the ESL traces. The power model factors are determined in a calibration step, based on a power curve and corresponding ESL traces from a reference scenario. Calibration can be performed using the least squares approach. More sophisticated variants remove redundancies from the traces first or constrain the power model factors. An extended version of the ESL power model supports different clock frequencies. It separates the total power consumption of a component into a part proportional to the ESL traces and a part proportional to the ESL traces multiplied by the clock frequency. By pre-multiplication of the traces with the clock frequency, the fixed-frequency approach can be extended to support the multi-frequency case. ESL tracing, power model calibration and power estimation for fixed- and multi-frequency variants have been implemented for VPs based on SystemC. A small extension of the SystemC kernel enables automatic collection of ESL traces from VPs without any modification of the VP source code. The power estimation method is evaluated using two extensive case studies. The first one evaluates the power estimation method for a Network on Chip with 16 nodes. The reference power data for calibration and comparison has been obtained from post-layout gate-level simulation. The VP matches the low-level implementation bit- and cycle-accurately. Using the more sophisticated calibration approaches results in estimation errors of less than 20% for most cases. The second case study uses a dual-core ARM Cortex-A9 application processor. Hardware measurements are used to obtain the reference power data. The performance of fixed-frequency and multi-frequency power models is evaluated for two VPs. The first one is a white box VP in which the internals of all component models are observable. The second one is a block box VP based on a closed-source processor simulator that allows only to trace the input and output ports. In all variants, the observed estimation error is below 10% for most of the test cases