Modeling, analysis and exploration of layers : a 3D computing architecture

Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.The design space of reconfigurable architectures spans a wide range, which allows different number of processing elements with different options on granularity, control structure, degree of specialization, scalability, regularity and programmability. For the theoretical point of view, these features can be captured by defining architectural flexibility, which quantifies how well a given architectural design point from the design space is matching a given application. If there is a good match, the application is efficiently executed and high performance and low power consumption is gained. In the view proposed in this work, architectures can be separated into small pieces of elementary hardware functions. These functions can be designed and rearranged such that the required function of the application is closely matched. The rearrangement of these small functions into larger functions is called functional reconfiguration. A categorization is also proposed into four functional domains: memory access, computation, communication and control flow. Via this concept, exploration, configuration and control of reconfigurable architectures becomes easier and allows design of a wide range of efficient architectures. To efficiently explore which configuration of elementary hardware components produces a design point that respects necessary constraints, a methodology is described based on High-Level Synthesis tools. Using this methodology, tens of architectural variants could be explored and evaluated. The guidelines presented in the methodology part of this work show how different types of architectures can be described and proposes two exploration directions: 1) weakly flexible applicationspecific architectures featuring elementary components specifically tailored for the architecture – targeted architectural flexibility –; and 2) architectures with a variable degree of flexibility, featuring a richer set of elementary functional components by which adaptation to changes in the application is possible – tunable architectural flexibility –. For the first direction, two WCDMA channel estimation algorithms, significantly different in performance and complexity, are targeted with a barely flexible architecture. The algorithms are analyzed carefully to expose common operations, parallelism and data movement patterns. Then, elementary hardware functions are created and an architecture is assembled which supports these two applications efficiently. High energy-efficiency gains are achieved with the resulting architecture supporting both algorithms, showing similar performance to architectural counterparts specialized to a single algorithm. The study is extended by fine-tuning the elementary functions with the addition of a reconfigurable fabric, yielding a closer application match and higher energy savings. For the second direction, a novel reconfigurable architecture called Layers is proposed, featuring a layered design with elementary hardware components tailored for different functional classes of an application: control flow, data movement, processing and memory access. By providing a pool of elementary functions for each class, a structure can be configured in each layer, that allows a close match to different application requirements. To demonstrate the degree of tunable flexibility that this solution achieves, an entire application domain is targeted. Multiple different applications from numerical linear algebra domain are mapped and evaluated on the architecture, achieving excellent scalability, performance and energy efficiency results. Scaling parallelism and resources of Layers, a clean trade-off of area vs. performance could be achieved for all tested applications while keeping energy constant, a result achieved by the high flexibility that the proposed structure provides. The work concludes by proposing enhancements to the Layers architecture: a force-directed scheduler and mapper for the computation layer of the architecture, which focuses on automating the application mapping process; and a new approach on automatically deriving and generating the architectural components for the control flow layer using a graph-theoretical approach contrasted by two manual designs