Parallele Prozessarchitektur für die Raum-Zeit-Entzerrung in breitbandigen Funksystemen mit adaptiven Gruppenantennen

Spatial multiplexing with adaptive antenna arrays will by applied to increase the data rate in future broadband radio systems. For an economic implementation of the required signal processing there is a demand for highly efficient parallel processors. Transformation in the frequency domain enables an efficient parallelization in conjunction with a flexible programmability. In this dissertation a corresponding application specific processor architecture is developed, requirements on word widths for fixed-point and floating-point arithmetic are evaluated and the implementation effort is shown in an exemplary application.As a basis for the application, first a transmission model is defined using a unified description of single- and multi-carrier modulation with optional spreading. Based on the transmission model the optimization problem of linear detection with minimum mean square error criterion is introduced. Several approaches to solve the problem are analyzed in relation to the underlying structure, kind and number of operations. All considered algorithms are characterized by independent processing of sub-carrier groups based on complex valued vector products. The characteristics of the designated applications result in a SIMD processor architecture using several identical arithmetical units (processor elements) configured by one common control unit. The application specific optimization of the processor elements for sequential calculation of complex valued vector products allows an efficient implementation of all considered algorithms near the peak processing power. The efficiency together with a simple structured programmability is obtained by the introduction of vector commands and the restriction to a linear command sequence.For two numerically critical algorithms the word widths of the arithmetical units are dimensioned using either fixed-point or floating-point arithmetic. Link level simulations based on a stochastic channel model show the influence of quantization errors and overflows in dependency of transmission parameters. The proposed processor architecture was implemented on a FPGA platform as part of a MIMO-WLAN demonstrator transmitting on a radio frequency near 10 GHz. By the analysis of resource and power consumption, the economic efficiency of the processor is evaluated for an FPGA implementation and estimated for an ASIC implementation. With a peak processing power of 17.6 GMAC/s, the processor is dimensioned for a raw bit rate of 800 Mbit/s using eight transmit and receive antennas. While feasibility is proved under high requirements, the scalability of the architecture by the number of processing elements allows the adoption of the results to other requirements