C compiler aided design of application specific instruction set processors using the machine description language LISA

The utilization of application specific instruction-set processors (ASIPs) allows for realizing System-on-Chip (SoC) circuits that are flexible, fast, and energy efficient at the same time. One way to reduce the high ASIP design effort is to create all software tools and hardware models from a single processor description written in a architecture description language (ADL). In this thesis LISA (language for instruction-set architectures) was used in a case study: The impact of incorporating a C compiler in the architecture exploration phase with respect to the processor architecture, the design time and the system reusability was analyzed. Another goal of this thesis was the (semi)automatic retargeting of a compiler from a LISA processor description. The case study pointed out the important role of the instruction scheduler in the ASIP design process. Therefore much effort was spent in finding algorithms for fully automatically retargeting this compiler component. Using a compiler, all assembly code can be generated. There is no need to rewrite or adapt the ASIP assembly code over and over again as it is usually done in the architecture exploration phase. With two target processors the expected speedup of the ASIP design time could be demonstrated. This also means that the system can much better be reused for other applications. The quality of the code generated by the retargeted compiler is a bit lower compared to handwritten compilers that were developed over many years. To overcome this problem a design goal of the retargeted compiler was modularity: It is still possible to integrate dedicated optimization modules in the (semi)automatically retargeted compiler. This way the code generator can not only be used for architecture exploration but for generating the production quality machine code of the application