Dynamic Coarse Grained Reconfigurable Architectures

Coarse grained reconfigurable processors have gained more popularity in the last years, as they introduce a new way for a dynamic and programmable execution similar to FPGA and tend to achieve the performance of application specific hardware. The reconfigurability on instruction level grants these architectures a big dynamicity and ability to embrace the diversity of the applications. Nevertheless, managing the hardware resources in the software prevents from undertaking many dynamical reactions needed by the reconfiguration task at runtime to be adaptive to the dynamic program execution. However, an adaptive architecture can face the diversity of applications dynamically in the hardware without any software manipulation. On the other hand, the need for more flexibility to manage the underlying hardware structures increases the demands on the configuration hardware unit. This work focuses on the design and optimization of reconfigurable coarse grained processors. In addition, it concerns with the implementation of the configuration task in the hardware. The Grid Alu Processor (GAP) is presented as baseline architecture for the design and optimization issues. We combine the characteristics of superscalar processors and coarse grained reconfigurable architectures to achieve a dynamicity and performance beyond that of out-of-order superscalar processors. Hence, the GAP comprises an in-order superscalar frontend and reconfigurable backend. A special configuration unit-fully integrated into the processor frontend instead of the issue stage-dynamically maps a conventional instruction stream at runtime to an array of reconfigurable functional units (FUs) inside the grid. A very important feature of our researched design is that it does not require a new ISA and special software or controlling processor to prepare and map the configurations to the hardware. It permits herewith the use of the well-known GCC compiler for superscalar architectures without any modifications of the generated binary files. To that, the in-order and simultaneous reconfiguration of dependent and independent instructions at runtime keeps the processor front-end simple and avoids the most large, unscalable hardware structures needed by out-of-order processors, for example: large issue windows and the needed hardware to control it, renaming structures, and reorder buffer.Rekonfigurierbare Prozessoren haben in der letzten Zeit an Gewicht gewonnen. Diese Architekturen erlauben die Rekonfiguration von einfachen sowie komplexen Ausführungseinheiten zur Laufzeit. Die Rekonfiguration auf Instruktionsebene bietet die Möglichkeit, ein dynamisches Design wie beim FPGAs zu entwickeln, allerdings mit viel besserer Performanz, ähnlich der von applikationsspezifischer Hardware. Die bisherigen rekonfigurierbaren Architekturen sind mit einem speziellen Softwaretool/Compiler verbunden, der für die Gewinnung von Konfigurationen sowie die Anwendung verschiedener Optimierungen zuständig ist. Diese Arbeit hingegen, befasst sich mit der Implementierung der Konfigurationstask in der Hardware sowie der Optimierung der Hardware im Grid der Ausführungseinheiten. Die Optimierungen dienen generell der Reduzierung der Hardwarekosten und der Performanzunterstützung