Computer Aided Design Solutions for Testability and Security

As technology down scaling continues, new technical challenges emerge for the Integrated Circuits (IC) industry. One direct impact of down-scaling in feature sizes leads to elevated process variations, which has been complicating timing closure and requiring classification of fabricated ICs according to their maximum performance. To address this challenge, speed-binning based on on-chip delay sensor measurements has been proposed as alternative to current speed-binning methods. This practice requires advanced data analysis techniques for the binning result to be accurate. Down-scaling has also increased transistor count, which puts an increased burden on IC testing. In particular, increase in area and capacity of embedded memories has led to overhead in test time and loss test coverage, which is especially true for System-on-Chip (SOC) designs. Indeed, expected increase in logic area between logic and memory cores will likely further undermine the current solution to the problem, the hierarchical test architecture. Further, widening use of information technology led to widened security concerns. In today\u27s threat environment, both hardware Intellectual Properties (IP) and software security sensitive information can become target of attacks, malicious tampering, and unauthorized access. Therefore, it is necessary for existing design flows to be properly improved to address these new challenges. Among possible options, mathematical optimization and novel architectural designs have time and again proved to be most promising approaches. In this work, we focus on developing new tools for this purpose by augmenting existing design flow. Implementation results on benchmarks proves proposed solutions to be effective and efficient