Performance of domino logic with dynamic body biased keeper

Domino logic have become extremely popular in the design of today's high performance processors because they offer fast switching speeds compared to static CMOS circuits. However, scale down the domino logic requires t hreshold voltage reduction and supply voltage scaling to maintain the performance, but it increases the subthreshold leakage currents exponentially . To solve this problem, keeper transistor is introduced. Domino logic with standard keeper however still has a proble m with a contention current. In this project, domino logic with dynamic body biased keeper technique is proposed to achieve high performance domino logic in terms of speed and power dissipation. The new design is proposed by adding a sleep transis tor, reduces the capacitive by half to 1fF and also connects a new resistor, R a in series with the load resistor, R L . The proposed design of domino logic with dynamic body biased keeper shows improvement of average 37.60% in terms of speed, 67.89% in terms of power dissipation and 80.00% in terms of power delay product when compared to domino logic with standard keeper. Meanwhile, the design also manage to enhance speed by 26.72%, reduce power by 67.81% and reduce power delay product by 76.44 % comparing to previous DBBK circuit