3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.Peer Reviewe
Aggressive scaling of transistor dimensions with each technology generation has resulted in increase...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
We summarize most of our studies focused on the main reliability issues that can threat the gain-cel...
3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute ...
Best DCIS Paper Award 20123T1D cell has been stated as a valid alternative to be implemented on L1 m...
With continued technology scaling, process variations will be especially detrimental to six-transist...
Memory circuits are playing a key role in complex multicore systems with both data and instructions ...
On-chip memories consume a significant portion of the overall die space and power in modern micropro...
ABSTRACT: This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light o...
Process variations have a large impact on device and circuit reliability and performance. Few studie...
As the semiconductor process technology continues to scale deeper into the nanometer region, the int...
Abstract—Evaluation results about area scaling capa-bilities of various SRAM margin-assist technique...
Aggressive technology scaling to 14 nm technology node increases variability in transistors performa...
In this thesis, we have investigated the impact of parametric variations on the behaviour of one per...
This paper analyses standard 6T and 7T SRAM (static random access memory) eell in light ol` process,...
Aggressive scaling of transistor dimensions with each technology generation has resulted in increase...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
We summarize most of our studies focused on the main reliability issues that can threat the gain-cel...
3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute ...
Best DCIS Paper Award 20123T1D cell has been stated as a valid alternative to be implemented on L1 m...
With continued technology scaling, process variations will be especially detrimental to six-transist...
Memory circuits are playing a key role in complex multicore systems with both data and instructions ...
On-chip memories consume a significant portion of the overall die space and power in modern micropro...
ABSTRACT: This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light o...
Process variations have a large impact on device and circuit reliability and performance. Few studie...
As the semiconductor process technology continues to scale deeper into the nanometer region, the int...
Abstract—Evaluation results about area scaling capa-bilities of various SRAM margin-assist technique...
Aggressive technology scaling to 14 nm technology node increases variability in transistors performa...
In this thesis, we have investigated the impact of parametric variations on the behaviour of one per...
This paper analyses standard 6T and 7T SRAM (static random access memory) eell in light ol` process,...
Aggressive scaling of transistor dimensions with each technology generation has resulted in increase...
Process parameter variations are expected to be significantly high in a sub-50-nm technology regime,...
We summarize most of our studies focused on the main reliability issues that can threat the gain-cel...