EM propagation within a computing package

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics as current chip multiprocessors are scaled. There have been plenty of works analyzing the WNoC paradigm from the physical, network and architecture layers. However, the propagation of millimeter waves inside a computing package is still not fully understood. As a result, aspects such as the path loss or the delay spread have not been precisely evaluated yet. This thesis tries to address this issue by accurately modeling a processor chip within a flip-chip package and investigating the wave propagation inside it. Then, through parametric studies, a potentially optimal configuration for 60 GHz WNoC is obtained. Finally, path loss and delay spread are evaluated for a set of representative scenarios, showing that chip-wide attenuation below -34,3 dB and channel capacity above 100 Gbps could be achieved.Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics as current chip multiprocessors are scaled. There have been plenty of works analyzing the WNoC paradigm from the physical, network and architecture layers. However, the propagation of millimeter waves inside a computing package is still not fully understood. As a result, aspects such as the path loss or the delay spread have not been precisely evaluated yet. This thesis tries to address this issue by accurately modeling a processor chip within a flip-chip package and investigating the wave propagation inside it. Then, through parametric studies, a potentially optimal configuration for 60 GHz WNoC is obtained. Finally, path loss and delay spread are evaluated for a set of representative scenarios, showing that chip-wide attenuation below -34,3 dB and channel capacity above 100 Gbps could be achieved.Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics as current chip multiprocessors are scaled. There have been plenty of works analyzing the WNoC paradigm from the physical, network and architecture layers. However, the propagation of millimeter waves inside a computing package is still not fully understood. As a result, aspects such as the path loss or the delay spread have not been precisely evaluated yet. This thesis tries to address this issue by accurately modeling a processor chip within a flip-chip package and investigating the wave propagation inside it. Then, through parametric studies, a potentially optimal configuration for 60 GHz WNoC is obtained. Finally, path loss and delay spread are evaluated for a set of representative scenarios, showing that chip-wide attenuation below -34,3 dB and channel capacity above 100 Gbps could be achieved