New embedded digital front-end for high resolution PET scanner

This work describes a new digital front-end for a high-resolution low-cost animal PET scanner which is currently under development. The advances in flexibility and size of modern FPGAs together with the release of new tools enable the integration of most of the front-end electronics in a single FPGA. The implemented system includes a small 32-bit RISC processor, several peripherals attached to the internal buses and a special DSP unit closely attached to the processor which is dedicated to the detection of the gamma events. On top of these, a small footprint real time operating system abstracts the underlying hardware, providing the mechanisms to combine on-chip slow control and data streamingThis work was supported in part by the FPU Research Grant from the Spanish Education and Science Ministry, by the Spanish Thematic Network IM3 (PI052204) and project TEC2004-07052-C02-02Publicad