Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit

Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to store each bit. Over the years, technology scaling of complementary metaloxide semiconductor (CMOS) devices has also resulted in the scaling of SRAM using minimum-size transistors. As transistor sizes scale down towards lower two-digit nanometer dimensions, CMOS circuits become more sensitive to radiations effects. High performances and high-density SRAMs are prone to radiation-induced single event upsets (SEU) which are dominated by secondary ions generated by nuclear collision events in the chip. The SEU generates are a soft error in transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 32nm CMOS technology towards SEU which is caused by the heavy ion impact with different Linear Energy Transfer characteristic (LET). This paper discussed the effect of LET towards drain node of NMOS and PMOS transistor for both 6T and 12T SRAM. The simulation results and analyses show that 6T SRAM circuit is vulnerable to SEU compared to 12T SRAM