Add to ORKGWe have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our method, a memory is shared between multiple physical links by using the multi-port memory. We evaluate and discuss the communication performance in the various situations. It is shown that the required number of memory banks required in multiport memory for 2D-torus and 2D-mesh networks is 8. Our proposed method yields high performance for both torus and mesh networks. Even this high performance is retained when the buffer size and the packet length are same
As multi-core systems begin to appear, their possible applications, parallel performance and on-chip...
[[abstract]]With the improvement of chip manufacture process, a single chip may contain many process...
This paper presents design trade-off and performance impacts of the amount of pipeline phase of cont...
We have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our...
In spite of much advancement in network-on-chip (NoC), area overhead further need to be explored and...
The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the l...
The memory is shared between multiple physical links by using the multi-port memory in the link shar...
Abstract. In this paper, we present an enhanced Network-on-Chip (NoC) architecture with efficient pa...
Abstract — On-chip routers typically have buffers dedicated to their input or output ports for tempo...
Abstract—Microarchitectural configurations of buffers in routers have a significant impact on the ov...
Network-on-Chip (NoC) architectures provide a scalable so-lution to the wire delay constraints in de...
Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A ...
Network line cards are experiencing ever increas-ing line rates, random data bursts, and limited spa...
Moore's prediction has been used to set targets for research and development in semiconductor indust...
Network line, cards are experiencing ever increasing line rates, random data bursts, and limited spa...
As multi-core systems begin to appear, their possible applications, parallel performance and on-chip...
[[abstract]]With the improvement of chip manufacture process, a single chip may contain many process...
This paper presents design trade-off and performance impacts of the amount of pipeline phase of cont...
We have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our...
In spite of much advancement in network-on-chip (NoC), area overhead further need to be explored and...
The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the l...
The memory is shared between multiple physical links by using the multi-port memory in the link shar...
Abstract. In this paper, we present an enhanced Network-on-Chip (NoC) architecture with efficient pa...
Abstract — On-chip routers typically have buffers dedicated to their input or output ports for tempo...
Abstract—Microarchitectural configurations of buffers in routers have a significant impact on the ov...
Network-on-Chip (NoC) architectures provide a scalable so-lution to the wire delay constraints in de...
Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for multi/manycore systems. A ...
Network line cards are experiencing ever increas-ing line rates, random data bursts, and limited spa...
Moore's prediction has been used to set targets for research and development in semiconductor indust...
Network line, cards are experiencing ever increasing line rates, random data bursts, and limited spa...
As multi-core systems begin to appear, their possible applications, parallel performance and on-chip...
[[abstract]]With the improvement of chip manufacture process, a single chip may contain many process...
This paper presents design trade-off and performance impacts of the amount of pipeline phase of cont...