플래시 SSD를 위한 운영체제 I/O경로 최적화

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 염헌영.Flash memory technology, in the form of flash solid-state drives (flash SSDs), is steadily replacing prior storage technology based on the value of affordable microsecond level random access memory with high bandwidth. While the cost per bit is now comparable with HDDs, the superior performance of SSDs are now replacing HDDs from our storage systems. However, due to the high latency variability, flash SSDs are yet to be a strong candidate to replace or complement DRAM based in-memory systems which are commonly seen in modern data centers under latency sensitive applications. Because of this variance, it can be challenging to meet both the IOPS and latency requirements for these latency sensitive applications. While the latency of flash SSDs are small enough to make software overheads of an I/O request not negligible, latency variance increases the overheads by magnifying the impact of context switches which harms both IOPS and latency capability of an I/O path. Also, the latency variance of flash SSDs is exposed in an uncontrolled fashion towards the applications which harm service level throughput of the data center. Such impact of variance has to be tolerated or controlled within the I/O path. To this end, this dissertation presents a set of host side OS I/O path optimizations which address the impact of latency variance of flash SSDs with the goal of using flash SSDs under latency sensitive applications. New I/O path designs based on two distinct approaches, which are 1) exploiting additional resource based on parallelism of multiple CPU cores or SSDs, and 2) exploiting the enhanced interactions between the host and the SSD are proposed to cope with the variance. While prior research has limitations on sacrificing one of either IOPS or latency to address variance, our I/O path designs achieve both IOPS and latency by trading additional resources. To reduce the software overhead caused by the variance, we implemented optimized AHCI based flash SSD device driver which enhances the IOPS capability of the I/O path by reducing the impact of context switches within the I/O completion path. This device driver achieved 100% IOPS enhancement over the original Linux I/O path. Also, an SSD extension was implemented on an SSD prototype platform which can further reduce the latency of individual I/O requests by overlapping scheduling delays with the actual I/O time. Here, the extension was able to introduce average 7us of latency reduction per I/O request without diminishing in system parallelism. To address the leakage of the latency variance, we developed a key-value storage engine as a flash SSD backend for a Memcached. The negative impact of latency spikes caused by write oriented operations was isolated from foreground read operations by exploiting redundant data copies placed on multiple SSDs. While this read-write separation technique provided moderate impact cutting the tail latency of the key value store to millisecond levels, dramatic reduction of was demonstrated by exploiting SSDs with the capability of controlling internal I/O operations such as garbage collection. The extensions achieved latency under 1 ms at the 99.9999th percentiles from the storage engine level.Chapter 1 Introduction 1 1.1 Motivation 1 1.1.1 Flash SSDs for Latency Sensitive Applications 2 1.1.2 The Impact of Flash SSD Latency Variability on the I/O Path 2 1.1.3 The Impact of Latency Variability Exposure 3 1.2 Dissertation Goals 4 1.3 Approach 4 1.4 OS I/O Path Optimizations for Flash SSDs 5 1.5 Contributions 7 1.6 Dissertation Structure 8 Chapter 2 Background 9 2.1 Adoption of Flash SSDs and the Impacton Our I/O path 9 2.2 Next Generation Memory Technologies 10 2.3 The Impact of Modern Flash SSDs 11 2.4 I/O Path for Flash SSDs 13 2.5 Related Work 14 2.5.1 Reconsidering the I/O path 14 2.5.2 Black-box Approaches 15 2.5.3 Cross-layer Approaches 16 2.5.4 Refactoring the I/O Path 17 Chapter 3 IOPS Improvement by Reducing the Impact of Context Switches 18 3.1 Introduction 18 3.2 Motivation 19 3.3 Design and Implementation. 21 3.3.1 HIOPS Hardware Abstraction Layer 22 3.3.2 HAL API Operations 23 3.3.3 OS I/O Path Optimizations 24 3.4 Evaluation 27 3.5 Summary 31 Chapter 4 Latency Reduction using SSD Internal Information 32 4.1 Introduction. 32 4.2 Motivation 33 4.2.1 System Impact of Modern SSDs 34 4.2.2 SSDs Unblinding the OS 35 4.3 Design and Implementation 36 4.3.1 Predicting the I/O Time of SSDs 36 4.3.2 OS I/O Path Optimizations 38 4.4 Evaluation 40 4.4.1 Experimental Setup 40 4.4.2 Results 41 4.5 Summary 43 Chapter 5 Tail Latency Reduction using Host Side GC Control and Multiple Devices 45 5.1 Introduction 45 5.2 Motivation 47 5.2.1 Large Scale Key Value Stores and Flash SSDs 47 5.2.2 Latency Spikes of Flash SSDs 48 5.2.3 Predictable latency, High IOPS but Higher Price 48 5.3 Design 49 5.3.1 Overview 49 5.3.2 SSD Control API 51 5.3.3 Multi-SSD Storage Engine 52 5.3.4 Latency Control 53 5.3.5 Scheduling I/O Operations 54 5.4 Evaluation 56 5.4.1 Implementation and Environment 56 5.4.2 Micro Evaluation 56 5.4.3 Full System Performance 59 5.5 Limitations 60 5.5.1 Additional Flash Chips 60 5.5.2 Non Standard API 60 5.5.3 Data Inconsistency upon Power Failures 61 5.5.4 Unbounded Write Latency 61 5.6 Summary 61 Chapter 6 Conclusion 63 6.1 Summary and Conclusions 63 6.2 Future Work 65 6.2.1 Extending the Scope of I/O Path Optimizations 65 6.2.2 Extended Use Cases of Host Assisting SSD Extensions 66 6.2.3 Applications for Different Technologies 67 Bibliography 69 초록 81Docto