2009 International Conference on Computational Science and Engineering // Vancouver, CanadaEmbedded systems often require small code size due to their tight memory constraints. Although the reduced encoding architectures such as the ARM THUMB or the MIPS-16 can successfully reduce the code size due to its half-sized instructions, they suffer from higher spills due to their shortened register fields which constrain available registers, thus affecting the code size and the performance negatively. One solution is reconstructing the original register file into the banked one and allowing only one bank to be active at a time using a bank change instruction. This can make all of the original registers available for register allocation, thus redu...
In conventional compilation, register allocation—the mapping of program variables to the registers o...
The register file is one of the critical components of current processors in terms of access time an...
International audienceStorage mapping optimization is a flexible approach to folding array dimension...
Bank switching in embedded processors having partitioned memory architecture results in code size as...
International audienceThis paper proposes a new microarchitectural scheme for reducing the hardware ...
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in progra...
The performance of the memory hierarchy has become one of the most critical elements in the performa...
Code compression is a field where compression ratios between compiler-generated code and subsequent ...
This paper presents a novel compiler directed technique to reduce the register pressure and power of...
It is important for compilers to generate executable code that is as small as possible, particularly...
Network processors are custom high performance embedded processors deployed for a variety of tasks t...
Multiple instruction issue processors place high demands on register file bandwidth. One solution to...
Banked register files have been proposed as a way to alleviate the latency and wiring overheads of c...
In compilation, register allocation is the optimization that chooses which vari-ables of the source ...
Multiple functional unit architectures have become increasingly widespread since they represent a vi...
In conventional compilation, register allocation—the mapping of program variables to the registers o...
The register file is one of the critical components of current processors in terms of access time an...
International audienceStorage mapping optimization is a flexible approach to folding array dimension...
Bank switching in embedded processors having partitioned memory architecture results in code size as...
International audienceThis paper proposes a new microarchitectural scheme for reducing the hardware ...
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in progra...
The performance of the memory hierarchy has become one of the most critical elements in the performa...
Code compression is a field where compression ratios between compiler-generated code and subsequent ...
This paper presents a novel compiler directed technique to reduce the register pressure and power of...
It is important for compilers to generate executable code that is as small as possible, particularly...
Network processors are custom high performance embedded processors deployed for a variety of tasks t...
Multiple instruction issue processors place high demands on register file bandwidth. One solution to...
Banked register files have been proposed as a way to alleviate the latency and wiring overheads of c...
In compilation, register allocation is the optimization that chooses which vari-ables of the source ...
Multiple functional unit architectures have become increasingly widespread since they represent a vi...
In conventional compilation, register allocation—the mapping of program variables to the registers o...
The register file is one of the critical components of current processors in terms of access time an...
International audienceStorage mapping optimization is a flexible approach to folding array dimension...