Design and analysis of an 8-bit SAR analog-digital converter

This report describes the author‘s final year project in the Circuits and Systems of Electrical and Electronic Engineering School in Nanyang Technological University. The main objective of this project is to analyze and develop the circuit design of an 8-bit Successive Approximation Register (SAR) Analog-to-digital Converter (ADC) using the Charter 0.18um processing technique. The design tool used is the Cadence Virtuoso schematic editor and Virtuoso Spectre simulator. The SAR ADC converts the analog signal to digital signal based on the binary search algorithm with comparably higher speed and resolution. In this project, an 8-bit SAR ADC with an internal current-steering DAC is designed to operate at 1.8V supply voltage and with the input range of 0.7V. The sampling frequency is 1MHz. The overall system‘s accuracy depends on the accuracy of the internal DAC. To achieve an accurate 8-bit data conversion, the stability of the reference voltage which is applied to the internal DAC and the accuracy level of the DAC are the key problems addressed. The low temperature sensitivity is obtained by employing an advanced curvature-compensation method in the bandgap reference design. For the different available implementations of the DAC, the sources of errors and the impact of these errors to the levels of system accuracy are analyzed and an appropriate topology is chosen. The simulation results show that the 8-bit SAR ADC is able to convert the 256 input segments within 0.7V into corresponding digital bits correctly at the 10MHz clock frequency. The average power dissipation is 4.06mW. Moreover, based on the same design approach, the system is upgraded to 10-bit resolution. The simulation results illustrate that this 10-bit system also exhibit an accurate behavior with an ideal current source to the DAC and the average power consumption is 10.948mW.Bachelor of Engineerin