Power-balanced instruction scheduling for pipelined VLIW architectures
- Xiao, Shu
DOIAbstract
The focus of this thesis is on techniques for minimizing power variation for the duration of the whole program.DOCTOR OF PHILOSOPHY (SCE
The focus of this thesis is on techniques for minimizing power variation for the duration of the whole program.DOCTOR OF PHILOSOPHY (SCE
Abstract In VLIW machines where a single instruction containsmultiple operations, the power consumpt...
10th International Symposium on Quality Electronic Design : March 16-18, 2009 : San Jose, CA, USAThe...
In this paper, an instruction-level energy model is proposed for the data-path of very long instruc...
[[abstract]]©2003 ACM-In this article, we investigate compiler transformation techniques regarding t...
[[abstract]]In this article, we investigate compiler transformation techniques regarding the problem...
[[abstract]]In this article, we investigate compiler transformation techniques regarding the problem...
[[abstract]]We investigate compiler transformation techniques for the problem of scheduling VLIW ins...
In this article, we investigate compiler transformation techniques regarding the problem of schedul-...
Instruction scheduling aims to reorder instructions in such a way that it covers the delay between a...
Very Long Instruction Word (VLIW) processors are wide-issue statically scheduled processors. Instru...
Abstract-- Many research groups have addressed code generation issues for a long time, and have achi...
This paper extends the state of the art by improving the energy characterization efficiency of state...
High-performance microprocessors are currently designed with the purpose of exploiting instruction l...
The advance in semiconductor technologies presents the serious problem of parameter variations. They...
Both total power consumption and peak power are the two critical issues in low power design. Dynamic...
Abstract In VLIW machines where a single instruction containsmultiple operations, the power consumpt...
10th International Symposium on Quality Electronic Design : March 16-18, 2009 : San Jose, CA, USAThe...
In this paper, an instruction-level energy model is proposed for the data-path of very long instruc...
[[abstract]]©2003 ACM-In this article, we investigate compiler transformation techniques regarding t...
[[abstract]]In this article, we investigate compiler transformation techniques regarding the problem...
[[abstract]]In this article, we investigate compiler transformation techniques regarding the problem...
[[abstract]]We investigate compiler transformation techniques for the problem of scheduling VLIW ins...
In this article, we investigate compiler transformation techniques regarding the problem of schedul-...
Instruction scheduling aims to reorder instructions in such a way that it covers the delay between a...
Very Long Instruction Word (VLIW) processors are wide-issue statically scheduled processors. Instru...
Abstract-- Many research groups have addressed code generation issues for a long time, and have achi...
This paper extends the state of the art by improving the energy characterization efficiency of state...
High-performance microprocessors are currently designed with the purpose of exploiting instruction l...
The advance in semiconductor technologies presents the serious problem of parameter variations. They...
Both total power consumption and peak power are the two critical issues in low power design. Dynamic...
Abstract In VLIW machines where a single instruction containsmultiple operations, the power consumpt...
10th International Symposium on Quality Electronic Design : March 16-18, 2009 : San Jose, CA, USAThe...
In this paper, an instruction-level energy model is proposed for the data-path of very long instruc...
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