Analysis of high-dielectric constant gate stack reliability for nanoscale CMOS devices application via scanning tunneling microscopy

The novelty of this study lies in the application of the scanning tunneling microscopy (STM), to study the electronic properties of the high-k gate stack at nanometre scale. The samples are the HfO2/SiOx and the Sc2O3/La2O3/SiOx gate stacks. Based on tunneling and energy band theory, the polycrystalline structure with grain size of ~27 nm of the high-k and the amorphous SiOx can be imaged independently at different biasing polarity. The polarity dependent STM current can therefore allow the demarcation of electronic traps in the high-k and the SiOx layer. This allows the evolution of electronic traps in each layer to be separately probed and studied under process condition change and electrical stress. By subjecting the high-k gate stack to different post-deposition annealing (PDA) temperatures, electrical weak spots and non-uniformity induced by PDA can be revealed by STM. Lateral resolved I-V characteristics extracted from leakage sites are found to exhibit either stress induced leakage current (SILC) or barrier height lowering (BHL) behaviors. STM observation of thermally induced localized low resistance path under tip injection and increase in leakage sites density in annealed gate stacks explain the reduced Weibull slope upon PDA.DOCTOR OF PHILOSOPHY (EEE