Design of high-speed low-dropout output capacitorless regulator for digital systems

Power management has increased enormously in the electronic industry with the prosperity of portable applications such as smart phones, laptops and PADs. Each digital system needs many power management blocks to supply various subsystems to increase the system stability and prolong the operational life time of the device. Low dropout (LDO) voltage regulators are commonly used circuits to supply stable and low voltage output. The traditional LDO regulator needs a large output capacitor, in the range of microfarads, to reduce the output voltage variation. This will increase the chip pin number and occupy a large area of the printed circuit board (PCB) which leads to the increase of cost. Hence, an output capacitor-less LDO regulator is presented in this dissertation. The proposed LDO regulator adopts dual-loop structure with self-adaptive topology and delay discharge circuit. It aims to apply for low-voltage systems that require fast transient LDO regulator in heavy capacitor load environment. It is designed to operate from 0.75V to 1.2V supply on the basis of UMC 65nm technology. It provides 0.5V output voltage with 49.4 pA quiescent current. The output voltage changes less than 50mV when the load current increases from OmA to IOmA in 100ps. The proposed LDO regulator can also drive a wide range of capacitance load from 470pF to lOnF. The simulation results have shown that the proposed LDO regulator have achieved the best figure-of-merit (FOM) value with respect to the published works. Besides, the LDO regulator has small settling time. It is also not sensitive to the process variation as well as load capacitance. As a result, the LDO regulator is useful for digital system for fully on-chip solution.Master of Science (Electronics