Clock data recovery circuits

This thesis presents the design and circuit implementation of a Clock Continuous Mode 2.5Gbps Data Recovery (CDR) circuit. The CDR is based on a new proposed dual-loop CDR architecture that doesn’t require the need of a lock detector. The operation is discussed in the report. The Foundary Design kit used is the Chartered Semiconductor Industry Compatible 0.18µm 1P6M CMOS process (CHRTIC018). Matlab Simulink is used to evaluate the system performance and Cadence Spectre simulation tool is used for circuit evaluation. This report also covers the basic fundamentals of clock data recovery process and examines some of the common existing structures. The first loop of the proposed architecture is a traditional 4-order PLL locking loop responsible for self-locking and providing a 2.5 GHz clock. The 2nd loop is the Data and 2.5GHz clock edge detecting loop using Alexander phase detector. The recovery process is mainly relied on the first loop to phase lock a 2.5GHz from a 10MHz reference signal. The 2nd loop then outputs a small charge pump current to upset the first loop to phase lock again. The process is repeated until when the clock and data are locked and recovered. The charge pump current then output from the 2nd loop is too small to upset the first loop, and hence an equilibrium state is reached. The new proposed CDR system simulation is first performed in Simulink to verify the system behaviour model, functionality and proof of concept. Based on Simulink system verification, circuit simulation and implementation is done by using Cadence Design tools. From this implementation, the proposed CDR architecture is realized capable of data locking at 2.5Gbps without the need of a lock detector.Master of Science (Integrated Circuit Design