Add to ORKGIn this project, the realization of a trenched SOI substrate is carried out, and the characterization of the CMP planarization together with a new polysilicon shallow trench isolation (STI) technique is studied.Doctor of Philosophy (EEE
Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime sili...
We have studied direct bonding and thinning of pre-etched silicon wafers. Silicon-on-insulator (SOI)...
The method involves initially depositing an oxide layer (112) on a structured layer (100) of the SOI...
In this project, the realization of a trenched SOI substrate is carried out, and the characterizatio...
First part aimed at producing varied planarization schemes that are suitable for both the Shallow Tr...
Silicon-on-insulator (SOl) structures comprised of fully dielectrically isolated device wells have b...
[[abstract]]A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a ...
Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced LOCO...
In the semiconductor device, the thick film SOI structure can separate various devices by dielectric...
An attempt is made at the preparation of silicon-on-insulator (SOl) substrates suitable for device f...
This paper discusses the fabrication of trench isolated CMOS using different filling materials. Prel...
Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical syst...
Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced loca...
An overview is given on the use of wafer bonding for formation of Silicon-On-Insulator (SOI) materia...
Shallow Trench Isolation (STI) holds many advantages to that of its predecessor isolation technology...
Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime sili...
We have studied direct bonding and thinning of pre-etched silicon wafers. Silicon-on-insulator (SOI)...
The method involves initially depositing an oxide layer (112) on a structured layer (100) of the SOI...
In this project, the realization of a trenched SOI substrate is carried out, and the characterizatio...
First part aimed at producing varied planarization schemes that are suitable for both the Shallow Tr...
Silicon-on-insulator (SOl) structures comprised of fully dielectrically isolated device wells have b...
[[abstract]]A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a ...
Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced LOCO...
In the semiconductor device, the thick film SOI structure can separate various devices by dielectric...
An attempt is made at the preparation of silicon-on-insulator (SOl) substrates suitable for device f...
This paper discusses the fabrication of trench isolated CMOS using different filling materials. Prel...
Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical syst...
Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced loca...
An overview is given on the use of wafer bonding for formation of Silicon-On-Insulator (SOI) materia...
Shallow Trench Isolation (STI) holds many advantages to that of its predecessor isolation technology...
Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime sili...
We have studied direct bonding and thinning of pre-etched silicon wafers. Silicon-on-insulator (SOI)...
The method involves initially depositing an oxide layer (112) on a structured layer (100) of the SOI...