Design and implementation of a digital integrated circuit for data transfer using VHDL

A final year project is a core module of School of Electrical and Electronic Engineering in partial fulfillment of the requirements for the degree of Bachelor of Engineering. This report details the tasks performed and the experience gained by the author during his final year working on this project. In this Final Year Project, Design and Implementation of a Digital Integrated Circuit for Data Transfer using VHDL, a bidirectional data communication path is set up between PC and FPGA. The main aim of this project is to relieve the design engineers of their expense, time, and reliability concerns of inventing their own PC connections. FPGA devices are becoming more and more popular for fast data processing because of the huge number of resources available on the board. The data sent to FPGA can be processed as per the requirement and then sent back to the PC. Opal Kelly USB 2.0 integration module based on the remarkably-capable Xilinx Spartan-6 FPGA is used in the project. A robust API for communication, Opal Kelly‟s Front Panel interface handles all the interaction between the software and FPGA hardware. Two projects have been designed for single data communication and multiple communications.Bachelor of Engineerin