Low power FFT processor IC

A low voltage low power FFT processor has been designed to meet the specifications required for application in an advance digital hearing enhancement device. This thesis will discuss the design, implementation and analysis of the proposed FFT processor. The processor is designed and implemented as a 128 point FFT processor. It operates with a supply voltage of 1.1V at a system frequency of 1MHz. The processor is implemented using a pipelined architecture and utilizes a radix-2 decimation in time FFT algorithm. This configuration is expected to deliver a design with the least power dissipation for the required specification.Master of Science (Integrated Circuit Design