Design of a low noise low voltage preamplifier

A low noise low voltage preamplifier is designed in this project. Using a 0.18 μm CMOS technology, a two-stage CMOS folded cascode operational amplifier with class AB output buffer is designed utilizing Cadence Custom IC Design Tool. The preamplifier is biased by a constant-transconductance bias circuit having wide-swing cascode current mirrors, which is to ensure that the preamplifier always work in saturation region. Lead compensation technique is introduced in circuit design in order to produce wider gain bandwidth and achieve stability at unity bandwidth. Ultimately, a preamplifier with high slew rate, high PSRR, high CMRR and low input referred noise level is created. Possessing a high gain of 76.53dB, gain bandwidth of 15.4MHz and phase margin of 75º, the designed preamplifier is proved to be capable in driving a load of 1k resistor in parallel with 1pF capacitor at a supply voltage of 1.8V.Bachelor of Engineerin