Development of automatic polishing for failure analysis of large microchips

Microelectronics failure analysis is important in determining the root causes of failure found in defective semiconductor packages. The true objective is to understand why the device fails, in an effort to implement corrective actions so as to ensure the functionality and reliability of such microelectronics system. Initial phase of failure analysis attempts to identify the type of failure faults through the use of electrical testing such as stressing or probing. Additionally, further physical analysis using various techniques such as scanning optical microscopy and x-ray imaging can be performed to localize the failure sites at the micrometer level. Regardless of whichever imaging techniques used, it is necessary for the IC chip package to undergo decapsulation process for easy access to the chips as well as exposing the die for subsequent polishing processes. Polishing is one of the methods used to delayer the thin metal films and dielectric materials in order to reveal the active components underlying beneath. In reality, current mechanical polishing of samples will typically result in a phenomenon known as corner rounding which is undesirable due to the loss of information at the edges. Thus, there is a need to better improve the mechanical polishing technique so as to reduce or possibly eliminate corner rounding effect. In this project, we attempt to explore how the different factors such as the pressure applied, accompanying with different curvature and diameter of the single head polishing tools can collectively affect the degree of corner rounding. Dependence on the frame surrounding the die has also been observed to influence the polishing mechanism significantly. These different parameters are thoroughly studied with the intention to better understand and improve the current mechanical polishing technique.Bachelor of Engineering (Materials Engineering