Design and monolithic realization of high-speed high-resolution analog-to-digital converters

This PhD program pertains to the design and monolithic realization of high-speed high-resolution Analog-to-Digital Converters (ADCs), particularly pipeline-based and Successive Approximation Register (SAR)-based architectures, for next-generation telecommunication systems. The primary objectives are to increase the speed and the resolution of these ADCs by means of innovative techniques/approaches, yet with minimal hardware and power overheads, and accommodating the ever-finer technology nodes. Interestingly, although the design art of pipeline and SAR ADCs are well established, several aspects of state-of-the-art designs and realizations remain inadequate. These inadequacies include the Multiplying Digital-to-Analog Converter (MDAC) in pipeline-based ADCs constraining the resolution, and the conversion algorithm of SAR-based ADCs limiting the speed. For the pipeline-based ADC, we propose, design, and monolithically realize a novel time-interleaved (×2) 11bit 1GS/s SAR-assisted MDAC-free pipeline architecture. At the system level, we propose to employ a front-end sample-and-hold to mitigate the problematic timing mismatch between the two time-interleaved channel ADCs. We further propose to predetermine the MSB (Most Significant Bit) outside the channel ADCs to substantially simplify the requirement of the channel ADCs. At the block level, we propose an innovative MDAC-free pipeline architecture for the channel ADCs where the MDAC is absent—to the best of our knowledge, this is the first-ever reported MDAC-free pipeline ADC architecture. The significance of the MDAC-free feature is particularly valuable to the pipeline ADC design as the well-reported critical issues arising from the MDACs are largely circumvented. Particularly, this leads to higher speed and higher accuracy, yet with potentially reduced design complexity. Further, this enables digital transmission between the pipeline stages, thereby substantially enhancing the accuracy and noise-immunity therein, and lending this architecture to ever-finer technology nodes due to its elimination of the analog residue amplification. The shortcoming, nevertheless, is the slightly increased hardware overheads. The SAR-assisted MDAC-free ADC prototype fabricated in 65nm bulk CMOS features SNDR ≥56dB across 500MHz Nyquist bandwidth at 1GS/s sampling rate with 230mW power dissipation. When benchmarked against state-of-the-art ≥11bits ≥1GS/s pipeline ADCs, the proposed pipeline-based ADC features a highly competitive Figure-of-Merit. For the SAR-based ADC realization, we propose a 2bit/step 10bit 400MS/s SAR ADC embodying a novel 2bit/step conversion scheme. By means of our proposed scheme, our proposed ADC offers three attractive features. First, only three capacitor arrays are required—to the best of our knowledge, the least number of capacitor arrays amongst reported CDAC-based 2bit/step SAR ADCs—leading to higher energy efficiency. Second, only two out of the said three capacitor arrays serve to sample the input signal, hence reducing the input loading. Third, the proposed ADC features an inherently symmetrical architecture with highly-matched interconnections, leading to enhanced system matching and higher accuracy. We further propose a high-speed high-accuracy dynamic comparator and a high-speed SA control logic to obtain high conversion rate. The SAR-based ADC prototype fabricated in 65nm bulk CMOS technology achieves SNDR >52dB and SFDR >63.7dB across 200MHz Nyquist bandwidth with 5.61mW power dissipation. When benchmarked against state-of-the-art CDAC-based 2bit/step SAR ADCs, the proposed SAR-based ADC features the smallest number of capacitor arrays and a highly competitive Figure-of-Merit.Doctor of Philosophy (EEE